1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly to a low power sense amplifier that can reduce power consumption by enabling the sense amplifier only during a data sense period.
FIG. 1 is a circuit diagram of a conventional sense amplifier. As illustrated in FIG. 1, the conventional sense amplifier comprises first and second PMOS transistors MP11, MP12 that are a latch, first and second NMOS transistors MN11, MN12 which amplify input signals from the input terminals IN11, IN12 and produce predetermined output signals through the output terminals OUT11, OUT12, and a third NMOS transistor MN13 which enables the first and the second NMOS transistors MN11, MN12 when the sense amplifier is enabled.
In the conventional sense amplifier as described above, when the sense amplifier enable signal SE is in a high state, i.e., in a data sensing period, a high state sense amplifier enable signal SE is applied to a gate of the third transistor MN13 to be turned on. Hence the first and the second NMOS transistors MN11, MN12 sense and amplify the input signals from the input terminals IN11, IN12 and produce output signals having different signal levels from each other first and second output terminals OUT11, OUT12 respectively.
On the other hand, when the sense amplifier enable signal SE is in a low state, i.e., not in a data sense period, the third NMOS transistor MN13 is turned off and thus the first and second transistors MN11, MN12 do not perform data sensing and amplifying operations.
FIG. 2 is a circuit diagram of a conventional sense amplifier for a nonvolatile memory device. The alternative sense amplifier as illustrated in FIG. 2 comprises a precharging part 25 that precharges a dummy line 22 connected to a dummy cell 21 and a bit line 24 connected to a memory cell 23 according to an equalizing signal /EQ; and a sense-amplifying part 26 that senses and amplifies voltages difference between the dummy line 22 and the bit line 24 and produces output signals via first and second output terminals OUT21, OUT22.
The precharging part 25 comprises first precharging means 25-1 comprising first through third PMOS transistors MP21-MP23 that precharges the dummy line 22; and second precharging means 25-2 comprising fourth through sixth PMOS transistors MP24-MP26 that precharges the bit line 24.
The sense amplifier 26 comprises seventh and eighth PMOS transistors MP27, MP28 that are a latch; first and second NMOS transistors MN21, MN22 that sense and amplify voltage difference between the dummy line 23 and the bit line 24; a third NMOS transistor MN23 that activates the first and the second transistors MN21, MN22, which is driven by a sense amplifier enable signal SE.
Also, the sense amplifier as illustrated in FIG. 2 further comprises pass transistors , i.e., fourth and fifth NMOS transistors MN24, MN25 driven by a reference voltage Vref from a reference voltage generator(not illustrated), in which the fourth and fifth NMOS transistors MN24, MN25 apply voltages from the dummy line 22 and the bit line 24 to the first and second NMOS transistors MN21, MN22 respectively; and a sixth NMOS transistor MN26 which equalizes according to an equalizing signal /EQ the dummy line 22 and the bit line 24.
The first and the second precharge means 25-1, 25-2 of the sense amplifier having a structure as illustrated in FIG. 2 precharge the dummy line 22 and the bit line 24 according to an equalizing signal /EQ outside a data sense period.
Also, the sixth NMOS transistor MN26 is activated by the equalizing signal EQ, and the dummy line 22 and the bit line come to be equalized to a same potential.
In this period, the third transistor MN23 of the sense-amplifying part 26 is turned off according to the low state sense amplifier enable signal SE, and the sense-amplifying operation of the first and second NMOS transistors MN21, MN22 do not take effect.
In one hand, during a data sense period, the third NMOS transistor MN23 of the sense-amplifying part 26 is turned on according to the high state sense amplifier enable signal SE. Hence, the first and second NMOS transistors MN21, MN22 sense and amplify the voltage from the dummy line 22 and the bit line 24 are applied to their gates respectively, and produce output signals of two different levels through the first and second output terminals OUT21, OUT22.
FIG. 3 is yet another conventional sense amplifier of a nonvolatile semiconductor memory device.
As illustrated in FIG. 3, the sense amplifier has a structure similar to that of FIG. 2. It comprises a precharging part 35 comprising first precharging means 35-1, which includes first through fourth PMOS transistors MP31.about.MP34 for precharging a dummy line 33 according to an equalizing signal /EQ, and second precharging means 35-2, which includes fifth through eighth PMOS transistors MP35.about.MP38 for precharging a bit line 34 according to the equalizing signal /EQ; and a sense-amplifying part 36 for sensing and amplifying voltages from the dummy line 33 and the bit line 34.
For the sense amplifier shown in FIG. 3, the sense-amplifying part 36 comprises two stages of a first sense-amplifying stage 36-1 and a second sense-amplifying stage 36-2. The first sense amplifying stage 36-1 comprises first and second NMOS transistors MN31, MN32 for producing output signals SOUT31, SOUT32 by sensing and amplifying the voltages from the dummy line 33 and the bit line 34; third and fourth NMOS transistors MN33, MN34 which are a latch; a fifth NMOS transistor MN35 for driving the third and fourth NMOS transistors MN33, MN34 according to the sense amplifier enable signal SE.
Also, the first sense-amplifying part of FIG. 3 further comprises a ninth PMOS transistor MP39 of which the sense amplifier enable signal SE is applied to the gate for maintaining voltage level of the output terminals SOUT31, SOUT32 in the same potential.
The second sense-amplifying stage 36-2 comprises tenth and eleventh PMOS transistors MP40, MP41 which are a latch; sixth and seventh NMOS transistors MN36, MN37 for sensing and amplifying the output signals SOUT31, SOUT32 of the first sense-amplifying stage 36-1; an eighth NMOS transistor MN38 for driving the sixth and seventh NMOS transistors MN36, MN37 according to the sense amplifier enable signal SE.
Furthermore, the sense amplifier of FIG. 3 further comprises a ninth NMOS transistor MN39 for equalizing the dummy line 33 and the bit line 34 according to the equalizing signal EQ; and tenth and eleventh NMOS path transistors MN40, MN41 driven by a reference voltage Vref from a reference voltage generator(not illustrated) for providing voltages from the dummy line 33 and the bit line 34 to the gates of the first and the second NMOS transistors MN31, MN32. The voltages from the dummy line 33 and the bit line 34 are the input signals for the sense-amplifying part 36.
The operation of the sense amplifier of FIG. 3 is the same as that of the sense amplifier of FIG. 2. The voltages from the dummy line 33 and the bit line 34 are sensed and amplified by the first sense-amplifying stage 36-1 of the sense-amplifying part 36. Then the output signals SOUT31, SOUT32 of the first sense-amplifying stage 36-1 is again sensed and amplified by the second sense-amplifying part 36-2. The final output signals having different voltage levels from each other are produced through the first and second output terminals OUT31, OUT32.
The sense amplifier enhances the sense margin by employing a two stage amplification of the voltages of the dummy line 33 and the bit line 34.
When the high state sense amplifier signal is introduced to the sense amplifiers of FIG. 1 through FIG. 3 to activate them, input data is sensed and amplified. The sensed and amplified data is then produced as the output data. To disable the sense amplifiers after the sensing and amplifying process, a low state sense amplifier enable signal must be introduced after a predetermined time the high state sense amplifier enable signal is introduced.
For a sense amplifier as described above to sense a data, adequate sense time must be provided. This is done by setting the pulse width of the sense amplifier enable signal large enough to meet the conditions described above.
However, as the current consumption is proportional to the pulse width, considerable power is consumed when each of the sense amplifier enable signal is set to have a width sufficiently large in one chip.